Study sheet: Microprocessor Architecture and Performance

📋 Course Outline

1. Microprocessor Role and Basic Architecture
2. Control and Processing Units
3. Instruction Execution Cycle
4. Instruction Set and Encoding
5. Programming Languages and Translation
6. Performance Measures
7. RISC and CISC Architectures
8. Pipeline and Advanced Architectures
9. Cache Memory and Pipeline Hazards
10. Specialized and Commercial Processors

📖 1. Microprocessor Role and Basic Architecture

🔑 Key Concepts & Definitions

• Microprocessor : A complex integrated circuit with very high integration that interprets and executes program instructions.

★ Must-know

• The basic architecture contains:
  • a control unit
  • a processing unit
  • registers
  • internal buses

Further detail

📌 General-purpose registers handle data at high speed through the internal data bus, whereas address registers or pointers are connected to the address bus.

💡 Memory Hook

UCT: control unit, processing unit, registers linked by buses

📖 2. Control and Processing Units

🔑 Key Concepts & Definitions

• Program Counter : A register initialized with the address of the first program instruction and containing the address of the instruction to execute.
• Arithmetic and Logic Unit : Performs logical operations such as AND, OR, comparison, and shifting, as well as arithmetic operations such as addition and subtraction.

★ Must-know

• The control unit fetches an instruction from memory, decodes its binary representation, executes it, and prepares the next instruction.

Further detail

• The status register contains 8-bit indicators including:
  • carry
  • auxiliary carry
  • sign
  • overflow
  • zero
  • parity

💡 Memory Hook

Control unit sequences instructions; processing unit performs operations

📖 3. Instruction Execution Cycle

★ Must-know

• Instruction execution consists of fetching the instruction, decoding it and finding its operand, then executing the instruction.

• During instruction fetch, the program counter places the next instruction address on the address bus, memory returns the instruction on the data bus, and the instruction register stores it.

Further detail

• During execution, the microprogram is executed, the flags are updated in the status register, and the control unit positions the program counter for the next instruction.

💡 Memory Hook

Fetch → decode and operand search → execute

📖 4. Instruction Set and Encoding

🔑 Key Concepts & Definitions

• Instruction Set : Describes all elementary operations that a microprocessor can execute and partly determines its architecture, especially that of the sequencer.

★ Must-know

• The four instruction groups are:
  • data transfer
  • arithmetic operations
  • logical operations
  • sequence control

📌 An instruction contains an instruction code indicating the operation and an operand field containing a datum or a reference to a datum in memory.

Further detail

• Register addressing uses data in a register, immediate addressing specifies the data value directly, and direct addressing uses data stored in memory.

💡 Memory Hook

TALC: transfer, arithmetic, logical, control instructions

📖 5. Programming Languages and Translation

🔑 Key Concepts & Definitions

• Machine Language : The binary language understood directly by the microprocessor, with each instruction represented by a specific bit sequence.
• Assembly Language : Close to machine language and uses rudimentary mnemonic instructions for data transfer, arithmetic, and logical operations.

📝 Essential Points

• A high-level program must be compiled into assembly language and then assembled into machine code before the microprocessor can execute it.

💡 Memory Hook

High-level language → compiler → assembler → machine code

📖 6. Performance Measures

🔑 Key Concepts & Definitions

• CPI : The average number of clock cycles required to execute one instruction for a given microprocessor.

★ Must-know

📐 Formula — The processing performance in MIPS is calculated by $MIPS = \frac{F_H}{CPI}$, with $F_H$ expressed in MHz.

Further detail

📌 Microprocessor performance can be increased by raising the clock frequency or reducing the average CPI through a suitable instruction set.

💡 Memory Hook

Higher frequency or lower CPI → greater processing performance

📖 7. RISC and CISC Architectures

★ Must-know

📌 CISC uses many complex instructions that require several cycles and a complex microcoded decoder, whereas RISC uses fewer simple instructions that generally execute in one cycle with a simpler decoder.

• RISC architectures generally use many registers, few addressing modes, and allow memory access through LOAD and STORE instructions, whereas CISC architectures generally use fewer registers and many addressing modes.

Further detail

• Studies cited in the course found that 80% of high-level-language processing used only 20% of the microprocessor instructions, motivating the RISC approach.

💡 Memory Hook

RISC: simple and fast instructions; CISC: complex and multi-cycle instructions

📖 8. Pipeline and Advanced Architectures

🔑 Key Concepts & Definitions

• Pipeline Architecture : Overlaps the stages of different instructions so that each processor component can be used during every clock cycle.
• Superscalar Architecture : Uses several parallel processing units to distribute and execute multiple instructions at the same time.

📝 Essential Points

📐 Formula — For n instructions requiring k cycles each, sequential execution requires n.k clock cycles, whereas a k-stage pipeline requires k+n-1 cycles and has gain $G = \frac{n.k}{k+n-1}$.

💡 Memory Hook

Pipeline stages overlap; superscalar units execute in parallel

📖 9. Cache Memory and Pipeline Hazards

🔑 Key Concepts & Definitions

• Cache Memory : A small, fast SRAM memory between the microprocessor and main memory that stores the most recent or frequently used information.

★ Must-know

📌 A cache hit occurs when the requested data or instruction is present in the cache, whereas a cache miss requires retrieval from main memory and storage in the cache.

• The three main pipeline hazards are:
  • structural hazards
  • data hazards
  • control hazards

Further detail

• Common average cache hit rates are approximately 80% to 90%.

💡 Memory Hook

Processor–memory latency → cache and hazard management

📖 10. Specialized and Commercial Processors

🔑 Key Concepts & Definitions

• Microcontroller : A minimum system on one chip containing a CPU, RAM, ROM, input/output ports, and specialized functions such as programmable counters or converters.
• Digital Signal Processor : Specialized for numerical signal processing such as FFT calculation, convolution, and digital filtering.

💡 Memory Hook

Microcontroller integrates a complete system; DSP specializes in digital signal processing

📊 Synthesis Tables

RISC and CISC comparison

Dimension	RISC	CISC
Instructions	Simple, generally one cycle	Complex, several cycles
Instruction format	Fixed	Variable
Decoder	Simple and wired	Complex and microcoded
Memory access	Mainly LOAD and STORE	Potentially all instructions
Registers and addressing	Many registers, few modes	Few registers, many modes